In a PWM system, conventionally, the output voltage ripple control usually uses hysteresis control, also called band-band control, to maintain the output voltage of the PWM system within a hysteretic band which is centered about the internal reference voltage. For further detail, FIG. 1 shows a typical PWM system 100 using the hysteresis ripple control, which comprises a control circuit 102 to switch a switching circuit 104 to produce an output voltage Vout. In the switching circuit 104, a high-side switch SW1 and a low-side switch SW2 are connected in series between an input voltage VIN and ground GND. The control circuit 102 provides a high-side switching signal HS and a low-side switching signal LS for a high-side driver 112 and a low-side driver 114 in the switching circuit 104, respectively, to produce a high-side driving signal UG and a low-side driving signal LG to respectively switch the switches SW1 and SW2, and an inductor current IL is thus produced to flow through an inductor L to charge a capacitor C so as to produce the output voltage Vout. In order to regulate the output voltage Vout, two serially connected resistors R1 and R2 are further provided in the switching circuit 104 to divide the output voltage Vout to thereby generate a feedback voltage FB for the control circuit 102, in which a first comparator 106 compares the feedback voltage FB with a valley voltage Vvalley to determine a first comparison signal PM, a second comparator 108 compares the feedback voltage FB with a peak voltage Vpeak to determine a second comparison signal Sc, and an SR flip-flop 110 has a set input S and a reset input R connected with the two comparison signals PM and Sc to thereby produce the two switching signals HS and LS, respectively.
FIG. 2 is a waveform diagram to exemplarily show various signals in the PWM system 100 of FIG. 1, in which waveform 116 represents the peak voltage Vpeak, waveform 118 represents the feedback voltage FB, waveform 120 represents the valley voltage Vvalley, waveform 122 represents the first comparison signal PM, waveform 124 represents the second comparison signal Sc, and waveform 126 represents the high-side driving signal UG. In the control circuit 102, once the feedback voltage FB decreases to a level not greater than the valley voltage Vvalley, as indicated at time t1 in FIG. 2 for example, the first comparator 106 sets the SR flip-flop 110 by the first comparison signal PM and accordingly, the high-side switching signal HS transits from low level to high level and the low-side switching signal LS transits from high level to low level. As a result, the high-side driving signal UG will be high level so as to turn on the high-side switch SW1 and the low-side driving signal LG will be low level so as to turn off the low-side switch SW2, by which the inductor current IL flows from the high-side switch SW1 to the capacitor C to thereby charge the capacitor C, and therefore the output voltage Vout increases. Since the feedback voltage FB is proportional to the output voltage Vout, it will raise as the output voltage Vout increases, and until the feedback voltage FB reaches the peak voltage Vpeak at time t2 as shown in FIG. 2, the second comparator 108 resets the SR flip-flop 110 by the second comparison signal Sc, such that the high-side switching signal HS transits from high level back to low level and the low-side switching signal LS transits from low level to high level. Accordingly, the high-side driving signal UG becomes low level to turn off the high-side switch SW1 and the low-side driving signal LG becomes high level to turn on the low-side switch SW2. Subsequently, the capacitor C is discharged and the output voltage Vout decreases. The feedback voltage FB then falls down in follow to the decreasing output voltage Vout until the next time it becomes not greater than the valley voltage Vvalley, the above operations will repeat again. The hysteresis control is so operated and, as shown in FIG. 2, the control circuit 102 will control the output ripple in a band range corresponding to that between the voltages Vvalley and Vpeak.
Even though the output voltage Vout may be corrected as quickly as the output filter allows and the output ripple is fixed, the conventional hysteresis PWM mode is difficult to be integrated into other topologies. For example, in Intel CPU Vcore applications, the output voltage has droop as the inductor current increases. If such system is to be integrated with the conventional hysteresis ripple control, the hysteretic band is required to be adjusted with the output load, i.e., the voltages Vvalley and Vpeak have to decrease when the PWM output loading increases, and vice versa, which is very difficult and unfeasible. Similarly, the conventional hysteresis mode is difficult to combine with low-gain current mode.
Therefore, it is desired a novel output ripple control circuit and method for a PWM system.